The present invention relates to a semiconductor device comprising a memory cell, which memory cell comprises:
a write transistor provided with a write transistor gate, a first write transistor electrode and a second write transistor electrode,
a read transistor provided with a read transistor gate, a first read transistor electrode and a second read transistor electrode,
a sense transistor provided with a sense transistor gate, a first sense transistor electrode and a second sense transistor electrode, the first sense transistor electrode being connected to the second read transistor electrode, the sense transistor gate being arranged as a floating gate, said floating gate being separated from the second sense electrode by a sense transistor oxide layer and from the second write transistor electrode by a tunnel oxide layer.
Such a semiconductor device is known from U.S. Pat. No. 5,761,116. FIG. 1 shows a basic electrical circuit for a memory cell known from this prior art document. The electrical circuit shows three transistors: a write transistor TWR, a read transistor TRE, and a sense transistor TSE. 
The write transistor TWR is provided with a drain and a source as indicated in FIG. 1. The drain is connected to a write bit line BLWR. The substrate of the write transistor TWR is grounded. The write transistor TWR is provided with a gate connected to a write word line WLWR. 
The read transistor TRE is provided with a drain and a source as indicated in FIG. 1. The drain is connected to a read bit line BLRE. The substrate of the read transistor TRE is grounded. The read transistor TRE is provided with a gate connected to a read word line WLRE. 
The sense transistor TSE is provided with a drain and a source 3 as shown in FIG. 1. The drain of the sense transistor TSE is connected to the source of the read transistor TRE. The substrate of the sense transistor TSE is grounded. The gate of the sense transistor TSE is connected to a floating gate FG.
The floating gate FG is separated from the source of the write transistor TWR by a thin tunnel oxide layer TUNOX.
Moreover, a control gate CG is provided, which is separated from the floating gate FG by a control gate oxide layer (or gate dielectric).
The operation of this prior art memory cell is summarized in table 1 below.
In the semiconductor device according to U.S. Pat. No. 5,761,116, the thicknesses of both the tunnel oxide layer TUNOX and the sense transistor oxide layer THINOX are about 8.0 nm (80 xc3x85).
In general, embedded semiconductor non-volatile memories often require a high reliability, a fast access time, and a low power consumption during programming and erasing operations. One of the ways to gain high speed is to scale down oxide layer thicknesses. However, a stress induced leakage current sets a lower limit for the sense transistor oxide layer THINOX and the tunnel oxide layer TUNOX. Reference is also made to K. Naruke et al. xe2x80x9cStress induced leakage current limiting to scale down EEPROM tunnel oxide thicknessxe2x80x9d, IEDM 1988, pages 424-427.
The object of the present invention is to provide a semiconductor device comprising a memory cell arrangement which inhibits SILC development in the sense transistor oxide layer THRNOX and thus reduces the lower limits of EEPROM gate oxides.
This object is achieved by means of a semiconductor device comprising a memory cell as defined at the outset wherein the memory cell comprises a voltage source arrangement arranged to provide the second sense transistor electrode with a predetermined voltage during programming and erasing, such that substantially no stress induced leakage current occurs in the sense transistor oxide layer.
By applying such an additional predetermined voltage to the second sense transistor electrode during programming and erasing, the voltage across the sense transistor oxide layer may be kept at such a low level that no (or substantially no) SILC occurs. This opens up the possibility to apply logic gate oxides in EEPROM devices and to make the processes and devices more compatible.
This basic idea is applicable both in single and double poly processes.
The sense transistor oxide layer and the tunnel oxide layer may have thicknesses between 5.0 and 10.0 run, preferably, however, between 6.0 and 9.0 run.
The predetermined voltage to be applied to the sense transistor oxide layer is preferably between 0.5 and 3.6 Volt.
The present invention also relates to a memory cell structure comprising a plurality of memory cells, each memory cell comprising:
a write transistor provided with a write transistor gate, a first write transistor electrode and a second write transistor electrode,
a read transistor provided with a read transistor gate, a first read transistor electrode and a second read transistor electrode,
a sense transistor provided with a sense transistor gate, a first sense transistor electrode and a second sense transistor electrode, the first sense transistor electrode being connected to the second read transistor electrode, the sense transistor gate being arranged as a floating gate, said floating gate being separated from the second sense electrode by a sense transistor oxide layer and from the second write transistor electrode by a tunnel oxide layer;
wherein a voltage source arrangement is arranged to provide the second sense transistor electrode of at least one selected memory cell with a predetermined voltage during programming and erasing, such that substantially no stress induced leakage current occurs in the sense transistor oxide layer of the at least one memory cell.
The present invention also relates to a method of controlling a memory cell, the memory cell comprising:
a write transistor provided with a write transistor gate, a first write transistor electrode and a second write transistor electrode,
a read transistor provided with a read transistor gate, a first read transistor electrode and a second read transistor electrode,
a sense transistor provided with a sense transistor gate, a first sense transistor electrode and a second sense transistor electrode, the first sense transistor electrode being connected to the second read transistor electrode, the sense transistor gate being arranged as a floating gate, said floating gate being separated from the second sense electrode by a sense transistor oxide layer and from the second write transistor electrode by a tunnel oxide layer;
wherein the method comprises the step of controlling a voltage source arrangement to provide the second sense transistor electrode with a predetermined voltage during programming and erasing, such that substantially no stress induced leakage current occurs in the sense transistor oxide layer.
Finally, the present invention relates to a method of controlling a memory cell structure comprising:
a write transistor provided with a write transistor gate, a first write transistor electrode and a second write transistor electrode,
a read transistor provided with a read transistor gate, a first read transistor electrode and a second read transistor electrode,
a sense transistor provided with a sense transistor gate, a first sense transistor electrode and a second sense transistor electrode, the first sense transistor electrode being connected to the second read transistor electrode, the sense transistor gate being arranged as a floating gate, said floating gate being separated from the second sense electrode by a sense transistor oxide layer and from the second write transistor electrode by a tunnel oxide layer;
wherein the method comprises the steps of:
selecting at least one predetermined memory cell
controlling the voltage source arrangement to provide the second sense transistor electrode of the at least one predetermined memory cell with a predetermined voltage during programming and erasing, such that substantially no stress induced leakage current occurs in the sense transistor oxide layer of the at least one predetermined memory cell.